A soft error means, differently from a hard error in which a specific portion of a circuit is permanently destroyed, a temporary malfunction from which an operation can be recovered, the temporary malfunction randomly occurring in a semiconductor chip. An incidence of a neutron ray being a secondary cosmic ray, an alpha ray from an LSI material or the like causes the soft error.
Presently, various countermeasures are considered against the soft error. As the most effective and general countermeasure, there is a method of adopting a circuit configuration which does not effect a system even if an error occurs. For example, in an Error Correction Code (ECC) circuit, an error may be corrected comparatively easily. However, these countermeasures involve area increase, and moreover, are difficult to be applied to a logic circuit. Therefore, if a soft error ratio increases with high integration density, there is a high possibility that a problem of the soft error becomes more serious than ever.
A general soft error avoiding method is described in Patent Document 1 below. As depicted in FIG. 32, a capacitance C is added to a data holding node of a latch circuit constituted by inverters 3201 and 3202 thereby preventing data inversion due to charge generation by a radiation ray. Application of the above method to the latch circuit involves performance degradation in terms of a set up time, a delay time and the like.
Further, in Patent Document 2 below, there is described a memory cell having: first and second data lines; a bistable flip-flop circuit provided between the first and second data lines and including a first inverter having an input from the first data line and a second inverter having an output to the second data line; a first addressable transmission gate connected between the first inverter and the first data line; a second addressable transmission gate connected between the second inverter and the second data line; and a third addressable transmission gate connected between the output of the second inverter and the input of the first inverter to control feedback between the first and second inverters.
Further, in Patent Document 3 below, there is described a data holding circuit having: a data holding unit holding data to be outputted; a pull-up path taking in and holding inputted data as a pull-up control signal in synchronization with a clock and pulling up data held in the data holding unit when the pull-up signal has one of values; and a pull-down path taking in and holding the input data as a pull-down control signal in synchronization with the clock and pulling down data held in the data holding unit when the pull down control signal has the other of the values, wherein the pull-up path is configured so that an error in which the pull-up control signal changes from the other of the values to the one of the values does not occur, wherein the pull-down path is configured so that an error in which the pull-down control signal changes from the one of the values to the other of the values does not occur, wherein an error from the one of the values to the other of the values having occurred in the pull-up path does not change a value held in the pull-down path and the data holding unit, and wherein an error from the other of the values to the one of the values having occurred in the pull-down path does not change a value held in the pull-up path and the data holding unit.
Further, in Patent Document 4 below, there is described a semiconductor integrated circuit device multiplexed by connecting a first latch circuit and a second latch circuit in parallel, wherein the first latch circuit has an input terminal to make the first latch circuit operate independently of the second latch circuit.                Patent Document 1: Japanese Laid-open Patent Publication No. 2005-191454        Patent Document 2: Japanese Laid-open Patent Publication No. 2006-59523        Patent Document 3: Japanese Laid-open Patent Publication No. 2006-60847        Patent Document 4: Japanese Laid-open Patent Publication No. 06-237151        